High performance semiconducting devices are continually being redesigned in order to increase processing speed and/or power. Each increase in processing speed and power generally carries a cost of increased size such that additional innovations must be made in order to minimize the size of the semiconducting devices. Manufacturers of semiconducting devices constantly try to improve product performance and reduce product size while minimizing production costs. A typical semiconducting device includes a die that is mounted on a substrate which functionally connects the die through a hierarchy of electrically conductive paths to the other elements that make up an electronic system.
Several methods have been employed to minimize the size of semiconducting devices. One method includes placing one or more dice onto an interposer and then folding the interposer to place one die on top of another.
One drawback of a semiconducting device that includes a folded interposer is that it is difficult to deliver power and/or signals to each of the dice because all of the conductive paths must be crowded through the fold in the interposer. Therefore, as the size of a semiconducting device decreases, it becomes more difficult to deliver signals and power to the dice through the fold in the interposer.
One way to address crowding within the fold in the interposer is to make the conductive paths smaller and place them closer together. However, when the conductive paths are small and crowded together, there is increased resistance, inductance and crosstalk within the conductive paths. This increased resistance, inductance and crosstalk causes unwanted signal degradation and power loss that inhibit the performance of the semiconducting device.